An integrated circuit is prone to damage by electrostatic discharge (ESD) throughout its life cycle, from manufacture to use in a product. An electrostatic discharge event is a high energy impulse having a voltage amplitude typically measuring thousands of volts that can physically and permanently damage a semiconductor device. In general, an electrostatic discharge event is coupled to circuitry of an integrated circuit through the input/output (I/O) of the device. The I/O are the interface of the integrated circuit for receiving/sending signals from off chip. The circuitry of the integrated circuit that couples to an I/O can be damaged unless protected by an electrostatic discharge protection circuit or device. ESD protection of an integrated circuit has always been a critical issue as the semiconductor industry continues the trend of shrinking transistor geometries to maximize circuit density per square inch of silicon. Forming a smaller transistor requires wafer processing having reduced critical dimensions and thinner material layers making it more sensitive to damage from ESD.
ESD devices are disabled during normal operation of an integrated circuit. An ESD event at one of the I/O triggers a corresponding ESD circuit to dissipate the energy of the ESD event before damage occurs to the integrated circuit. Typically, this is achieved by enabling a device or devices having an extremely low impedance coupled to ground. In other words, the high voltage impulse is shunted to ground through the ESD circuit. The ESD circuit is disabled once the energy is dissipated or the voltage at the I/O falls to a safe level. Ideally, an ESD circuit does not load the I/O significantly when disabled, responds rapidly to an ESD event, takes up minimum area, and has a low impedance when enabled.
FIG. 1 is a schematic diagram of a prior art electrostatic discharge (ESD) protection circuit 10. ESD protection circuit 10 is a model of an integrated device structure that is coupled to the I/O pads of an integrated circuit to protect against electrostatic discharge. ESD protection circuit 10 has a terminal 15 and a terminal 20. Terminal 15 couples to circuitry of an integrated circuit and corresponds to an I/O of the device. The terminal 20 of ESD protection circuit 10 is coupled to ground. ESD protection circuit 10 comprises a transistor 25, a zener diode 30, and a resistor 35. Transistor 25 includes a collector coupled to terminal 15, a base, and an emitter coupled to terminal 20. Zener diode 30 has a first terminal coupled to terminal 15 and a second terminal coupled to the base of transistor 25. A resistor has a first terminal coupled to the base of transistor 25 and a second terminal coupled to terminal 20. In an embodiment of ESD protection circuit 10, zener diode 30 is integrated into the structure of transistor 25.
An integrated circuit typically has a specified voltage range under which it can operate. A voltage applied to terminal 15 within the specified voltage range will not damage the internal circuitry of the integrated circuit coupled to the I/O. In general, the specified voltage range is conservative and a greater voltage (but less than BVDSS) can be applied to terminal 15 without damage. Zener diode 30 is designed to have a breakdown voltage greater than the specified voltage range. Zener diode 30 conducts no current when a voltage applied to terminal 15 is within the specified voltage range. Resistor 35 couples the base of transistor 25 to ground under this condition. Transistor 25 is off because the base-emitter junction is not forward biased having both the base and the emitter coupled to the same voltage potential (ground). Thus, transistor 25 and zener diode 30 are disabled and conduct no current under normal operation of the integrated circuit.
An ESD event coupled to terminal 15 is a fast rise time, voltage impulse, having a magnitude that measures thousands of volts if the impulse is not attenuated. ESD protection circuit 10 is enabled by the voltage impulse and dissipates the energy corresponding to the electrostatic discharge before damage to the circuitry coupled to terminal 15 occurs. An impact ionization current is generated in zener diode 30 when the voltage impulse exceeds the breakdown of the device.
The impact ionization current increases as avalanche multiplication occurs in zener diode 30. The impact ionization current from zener diode 30 couples through resistor 35 and generates a rising voltage at the base of transistor 25. Transistor 25 is enabled when the base voltage rises to a voltage that forward biases the base-emitter junction of the device. Transistor 25 is a high current gain device. Once enabled, transistor 25 rapidly sinks current from the ESD event thereby dissipating the energy of the impulse which results in the voltage being clamped to a level that protects the circuitry coupled to terminal 15.
FIG. 2 is a cross-sectional view of the prior art electrostatic discharge (ESD) protection circuit 10 of FIG. 1. In general, ESD protection circuit 10 couples to and is formed in proximity to an I/O pad of an integrated circuit. ESD protection circuit 10 has terminal 15 coupled to the I/O pad of the integrated circuit and terminal 20 coupled to ground. An n-type epitaxial layer 110 overlies a p-type substrate 105. An isolation region 120 defines the active area in which ESD protection circuit 10 is formed. Isolation region 120 is a p-type region that is formed in a ring shape and is coupled to ground. The active area is interior to the ring shape.
Transistor 25 of FIG. 1 comprises a base region 130, an emitter region 145, and a collector. The collector is epitaxial layer 110 in the active area. Transistor 25 is a high current gain vertical transistor. Base region 130 is p-type and is formed in epitaxial layer 110. Emitter region 145 is n-type and is formed in base region 130. A p-type region 140 is formed at the surface of base region 130 in a ring shape and surrounds emitter region 145. P-type region 140 is a low resistance base contact to base region 130. P-type region 140 and emitter region 145 are coupled to terminal 20. As mentioned previously, terminal 20 is coupled to ground.
A buried layer 115 and n-type region 125 combine to form a low resistance path for collector current of transistor 25. Buried layer 115 underlies base region 130 and is formed at the interface between substrate 105 and epitaxial layer 110. N-type region 125 is a ring shaped region that surrounds base region 130. N-type region 125 is a deep n+ region formed in epitaxial layer 110 in the active area that forms a low resistance path from a surface of epitaxial layer 110 to buried layer 115. A heavily doped n-type region 135 is formed in region 125 that couples to terminal 15 of ESD protection circuit.
Zener diode 30 of FIG. 1 comprises a p-type region 150, epitaxial layer 110, and n-type region 125. P-type region 150 overlies a boundary of base region 130 and epitaxial layer 110. P-type region 150 couples to base region 130 and is formed in a ring shape around the periphery of base region 130. P-type region 150 has a higher doping concentration than base region 130. As shown in FIG. 1, zener diode 30 is coupled in parallel with the collector-base of transistor 25. The spacing between p-type region 150 and n-type region 125 and the doping concentrations of the device components of zener diode 30 play a role in determining what voltage zener diode 30 breaks down.
Resistor 35 of FIG. 1 corresponds to the inherent resistance of base region 130. In an ESD event, impact ionization current is generated by zener diode 30 when the breakdown voltage of zener diode 30 is exceeded. The impact ionization current is coupled to base region 130. Note that both emitter region 145 and p-type region 140 are coupled to ground through terminal 20 of ESD protection circuit 10. The inherent resistance of base region 130 produces a voltage drop as impact ionization current is conducted that forward biases the base-emitter junction of transistor 25. Upon enabling transistor 25, a portion of the impact ionization current is base current for the device. The base current is multiplied by the current gain of transistor 25 which rapidly dissipates the energy of the ESD event and clamps the voltage from exceeding a value that can damage circuitry coupled to terminal 15. The voltage at terminal 15 falls as transistor 25 dissipates the energy of the ESD event. Zener diode 30 stops conducting current when the voltage at terminal 15 falls below the breakdown voltage of the device. Transistor 25 is disabled when deprived of the current from zener diode 30 thus returning to the state prior to the ESD event with no current being conducted by zener diode 30 and transistor 25.
FIG. 3 is a graph of a transmission pulse line characteristic corresponding to ESD protection circuit 10 of FIG. 2. Transmission pulse line testing provides a pulse similar to an ESD event to an ESD protection circuit. The voltage and current coupled to the ESD protection circuit is monitored. A curve on the graph relates to measurements on an ESD protection circuit similar in structure to that shown in FIG. 2 and measuring 52.5 microns on a side. Voltage is displayed on the x-axis and current on the y-axis.
The voltage impulse is clamped to a voltage magnitude less than 50 volts as the zener diode breaks down providing impact ionization current to enable the transistor. The voltage rapidly falls to approximately the breakdown voltage of the zener diode plus a base-emitter junction voltage. The test equipment measures the maximum current that can be handled by ESD protection circuit before failure. The point of failure is represented by dot 210 on the curve which corresponds to a current slightly less than 4000 milliamperes.
Although not indicated by the graph, the failure mechanism typically results in damage at the base terminal of the ESD protection circuit. As mentioned previously, the transistor tested corresponds to the device shown in FIG. 2. The transistor tested is a vertical device comprising emitter region 145, base region 130, and epitaxial layer 110 (collector). The device structure shown also has parasitic lateral transistor component that is inherent to the design. It is believed that the failure at the base terminal of the device occurs due to high currents flowing near the surface of the transistor due to currents from the zener diode and the lateral transistor that couple to the base terminal. An ESD event of substantial energy produces a current at the base terminal due to the circuit structure that causes a failure in the ESD protection device.
Accordingly, it is desirable to provide an electrostatic discharge protection circuit capable of suppressing higher energy electrostatic events. It would be beneficial if the electrostatic discharge protection circuit had a smaller footprint. It would be of further benefit if the electrostatic discharge protection circuit did not require any special manufacturing steps. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.